1. Field of the Invention
The present invention relates to a switching power supply for supplying electric power to an electronic device.
2. Description of the Related Art
An example of a switching power supply is described below with reference to FIG. 8 and FIG. 9. In FIG. 8, a direct-current voltage Vin charged in a primary electrolytic capacitor C1 is supplied to a drain terminal of a field effect transistor FET1 serving as a switching element via a primary winding of a transformer T1. A source terminal of the field effect transistor FET1 is connected to a primary electrolytic capacitor C1 via a current detection resistor Ris. A secondary winding of the transformer T1 is connected to a secondary electrolytic capacitor C2 via a secondary rectifier diode D3. A direct-current voltage Vout stored across the secondary electrolytic capacitor C2 is output as an output voltage from the switching power supply. The direct-current voltage Vout is divided by a resistor R3 and a resistor R4, and a divided voltage is supplied to a reference terminal of a shunt regulator IC2. A cathode terminal of the shunt regulator IC2 is connected to an LED of a photocoupler PC-FB. A phototransistor of the photocoupler PC-FB is connected to a PWM control module IC1. A collector voltage of the phototransistor of the photocoupler PC-FB serves as a feedback signal (also referred to as a FB signal) of the output voltage Vout of the switching power supply. The FB signal is pulled up by a resistor R1 in the PWM control module IC1 and input to an inverting input terminal of a PWM amplifier AMP1. A non-inverting input terminal of the PWM amplifier AMP1 is supplied with a triangle wave signal (also referred to as an OSC signal) from a triangle wave signal generator.
Referring to FIG. 9, when the voltage of the OSC signal is higher than the voltage of the FB signal, as at time t0, the PWM amplifier AMP1 outputs a high-level (H-level) signal. The signal output from the PWM amplifier AMP1 is supplied to an input terminal of an OR circuit. The other input terminal of the OR circuit is supplied with a Q output from a flip-flop circuit FF. At time t0, the Q output of the flip-flop circuit FF is at a low level (also referred to as an L level) as explained later, and thus an output of the OR circuit is at a high level (also referred to as an H level). The output from the OR circuit is supplied to an output buffer circuit including a field effect transistor FET2 which is a P-channel MOSFET serving as a switching element and a field effect transistor FET3 which is an N-channel MOSFET also serving as a switching element. Thus, an output signal (also referred to as an OUT signal) from the PWM control module IC1 is at an L level. The OUT signal is supplied to a gate terminal of the field effect transistor FET1. Thus, the field effect transistor FET1 turns off.
At time t1, if the voltage of the OSC signal becomes lower than the voltage of the FB signal, the output of the PWM amplifier AMP1 goes to the L level, the output of the OR circuit goes to the L level, and the OUT signal goes to the H level. Thus the field effect transistor FET1 turns on and a drain current Id flows through the field effect transistor FET1. At time t2, if the voltage of the OSC signal again becomes higher than the voltage of the FB signal, the output of the PWM amplifier AMP1 goes to the H level, the output of the OR circuit goes to the H level, and the OUT signal goes to the L level. Thus the field effect transistor FET1 turns off, and the flowing of the drain current Id stops.
Then at time t3 and in a following period, the output current Iout of the switching power supply increases and the output voltage Vout falls down slightly. In response, the shunt regulator IC2 reduces the current flowing through the LED of the photocoupler PC-FB. As a result, the FB signal increases and the length of the ON period (also referred to as an ON pulse width) from t4 to t5 of the field effect transistor FET1 increases. As a result, the output voltage Vout increases slightly.
The PWM control module IC1 controls the ON period of the field effect transistor FET1 (by the PWM control) to stabilize the output voltage Vout in the above-described manner.
The switching power supply of the above-described type usually has an overload protection circuit. More specifically, the overload protection circuit operates such that the drain current Id of the field effect transistor FET1 is detected by the current detection resistor Ris connected to the source terminal of the field effect transistor FET1, and if the drain current Id becomes equal to a predetermined value and more specifically Vref/Ris, the field effect transistor FET1 is turned on whereby a load current of the switching power supply is limited to a predetermined rated value Ip or less.
The operation of the overload protection circuit is described in further detail below. The drain current Id of the field effect transistor FET1 is converted into a voltage by the current detection resistor Ris and supplied, as a current detection signal IS, to a non-inverting input terminal of a current sense amplifier AMP2 in the PWM control module IC1. An inverting input terminal of the current sense amplifier AMP2 is connected to a constant voltage source Vref. When the value of the drain current Id is less than Vref/Ris as in a period from t0 to t8, the voltage of the current detection signal IS is lower than Vref, and the output of the amplifier AMP2 is at the L level. The output of the amplifier AMP2 is supplied to an S input terminal of the flip-flop FF.
An R input terminal of the flip-flop FF is supplied with the OSC signal so that the flip-flop FF is reset when the OSC signal has a peak value. Thus, the flip-flop FF is reset at times t1, t4, t6, and t8 at which the OSC signal is at its peak. During this period, the S input terminal of the flip-flop FF is at the L level, and thus the Q output of the flip-flop FF is at the H level. The Q output of the flip-flop FF is supplied to the OR circuit. Thus, during the period from time t0 to time t8, the switching operation of the field effect transistor FET1 does not receive any influence. At time t9, if the value of the drain current Id reaches Vref/Ris, the voltage of the current detection signal IS becomes higher than Vref, and the output of the amplifier AMP2 goes to the H level. As a result, the Q terminal of the flip-flop FF goes to the H level, the output of the OR circuit goes to the H level, and the OUT signal goes to the L level, and thus the field effect transistor FET1 turns off. At time t10, the flip-flop FF is reset, and the field effect transistor FET1 again turns on. However, when the drain current Id reaches Vref/Ris (at time t11), the field effect transistor FET1 turns off. As described above, the drain current Id is limited to the predetermined value equal to Vref/Ris. Therefore, the output current lout of the switching power supply is also limited to a predetermined value Ip. A description of the above-described technique may be found, for example, in Japanese Patent Laid-Open No. 2004-312901.
The above-described switching power supply has a following problem.
The drain current Id of the field effect transistor FET1 has an intermittent triangular waveform. Therefore, the current flowing through the current detection resistor Ris also has an intermittent triangular waveform. In view of the above, usually, a resistor having high pulse resistance is used as the current detection resistor Ris. For example, a wire wound resistor formed by winding a metal wire into the form of a coil as shown in FIG. 10A a film resistor formed by cutting a helical slit in a cylindrical resistor film as shown in FIG. 10B.
By virtue of their coil structure, the resistors of these types have inductance Lis. The inductance Lis of the current detection resistor Ris influences the operation as described below with reference to FIGS. 11 and 12.
At time t21, if a gate-source voltage Vgs of the field effect transistor FET1 increases beyond a gate threshold voltage Vth, the drain current Id starts to flow and the value of the drain current Id gradually increases. The drain current Id also flows through the inductance Lis of the current detection resistor Ris. At time t22, if the gate-source voltage Vgs falls down below the gate threshold voltage Vth, the drain current Id abruptly decreases. This causes a back electromotive force Vs to occur across the inductance Lis. This back electromotive force Vs occurs such that the polarity thereof is negative at the source terminal of the field effect transistor FET1 and positive at the GND terminal of the PWM control module 101. The FET3 in the PWM control module 101 includes a body diode D1. Thus, the back electromotive force (back electromotive voltage) Vs is applied between the gate and the source of the field effect transistor FET1 through a path including a GND terminal of IC1→the body diode D1→the gate of the field effect transistor FET1, as indicated by a broken line in FIG. 11. In response, as indicated at time t23 in FIG. 12, the gate-source voltage Vgs of the field effect transistor FET1 increases beyond the threshold voltage Vth, which causes the field effect transistor FET1 to again turn on. As a result, the drain current Id starts to flow. In this state, the drain-source voltage Vds of the field effect transistor FET1 has a very high value, which may cause heat to be generated in the field effect transistor FET1. In the worst case, the field effect transistor FET1 is destroyed.
In view of the above-described problem, the present invention provides a technique to reduce heat generated in a switching element caused by back electromotive force generated by inductance of a current detection resistor.